Generally in integrated circuit design, integrated circuit chip layouts are commonly shrunk, or scaled, to smaller technology nodes to reduce product costs and extend the product's life cycle. Processes that realized this shrinking or scaling are generally known as shrink technology. However, these processes are not without their drawbacks.
Known processes typically require a designer to scale down by a fixed factor a taped-out chip layout from one technology node to a smaller technology node. Scaling down a layout in this manner usually results in process variations between the technology nodes and in performance variation. Some process variations that may arise are problems in gate processing, such as forming gate spacers, gate oxide thickness, metal thickness, etching bias, mask making, and optical proximity correction (OPC). Performance variations could be changes in timing of the circuit caused from changed capacitances and resistances of the scaled down devices and metal layers, traces, and the like.
Any problems in the scaled down layout generally would be corrected manually through an engineering change order (ECO). The problems typically would be discovered during implementation, such as by using electronic design automation (EDA) software. Then once the problem was discovered, an ECO would generally require a designer to manually fine tune the layout. Then, the layout would be implemented again, such as by using an EDA, to determine if the problem remains. This would continue until the problem was solved. These processes thus generally use many man-hours to bring the scaled down layout to tape-out. Accordingly, there is a need in the art to optimize the migration of integrated circuit chip layouts to smaller technology nodes without requiring the inefficient use of many man-hours.